1. Field
Example embodiments relate to a semiconductor memory device, for example, a semiconductor device including distributed data input/output lines.
2. Description of the Related Art
A word line and a bit line may generally be arranged so as to intersect at right angles on a memory cell array of a semiconductor memory device, for example, Dynamic Random Access Memory (DRAM). The bit line may be connected to an input/output (I/O) line via which data may be input or output with a switch circuit. Also, a memory cell that may store data may be located in a region where the bit line and the word line intersect. An increase in the capacity of a semiconductor memory device may be accompanied by higher densities and a peripheral circuit to control data written to or read from the memory cell.
For higher-speed operation of I/O lines in a semiconductor memory device, the I/O lines may be arranged according to a hierarchical I/O line structure, in which they may be divided into local and global I/O lines. A hierarchical I/O line structure may reduce the loading on the I/O lines, and may increase bandwidth for a more highly-integrated semiconductor memory device. The bandwidth may refer to the amount of data that may be transmitted in a given period of time, for example, per second.